(1) Field of the Invention
The invention relates generally to data storage in semiconductor memory devices, and more particularly, to Random Access Memory (RAM) devices within Liquid Crystal Display (LCD) interface circuits with asynchronous, collision free read and write data access thereto, during simultaneous transmission of serial data input.
(2) Description of the Prior Art
Graphical LCD displays such as those used e.g. on mobile information terminals etc. need a specific controller circuit for their proper operation. Such LCD controllers are used to control the operation of the LCD display and supply the display drivers with appropriate data. An important feature of these LCD display interfaces is the use of RAM for data storage purposes. It is also well known to employ LCD controllers with asynchronous serial data input. A common problem, which must be overcome in such an LCD interface, is the possibility of simultaneous read-write access to the same data RAM, because the LCD controller reads data periodically and completely unaware of the randomly incoming serial data. With commercially available LCD interface chips the problem of asynchronous read and write access to RAM usually is solved utilizing Dual-Port RAM (DPRAM) or Single-Port RAM (SPRAM) in conjunction with additional output buffers.
Asynchronous signifies in this context, that read and write accesses to RAM may occur independently in time i.e. asynchronously to each other. Therefore, it is necessary to avoid collisions of data access in time, which would in consequence lead to corrupted data in RAM. Generally used thereby, for well-known technical reasons, is Static RAM (SRAM).
In the current art, there are two techniques for guaranteeing valid, non-corrupted data in SRAM. In the first technique, a Dual-Port SRAM (DPRAM) is employed. This approach has the advantage of a simple straightforward design, since input ports and output ports a strictly separated, i.e. even simultaneous read-write access does not lead to corrupted data in memory. Unfortunately, the internal chip structure is somewhat more complex and thus requires a larger amount of chip area. The second technique uses Single-Port SRAM (SPRAM) with buffered output. However, this solution requires one additional data register for each data line. It would be advantageous to utilize the simpler SPRAM instead of DPRAM and avoid data access collisions by some other means instead of additional buffering. Considerations made in connection with SPRAM use furnished some interesting solutions until now, but none of which took the onset presented here.
Several prior art inventions describe means/methods for avoidance of data access collisions at SPRAM use.
U.S. Pat. No. 5,974,482 to Gerhart describes a single-port first-in-first-out device having an overwrite protection capability. The FIFO device includes a single-port memory for storing data from a host processor. The single-port memory is addressed in a sequential and non-random manner. Control circuitry coupled to the counter and the memory allows for the reading/writing of host data from/to the single-port memory. Write protect circuitry prevents host writes to the single-port memory by entering a write protect state.
U.S. Pat. No. 6,314,047 to Keay et al. shows a low cost alternative to a large DPRAM using a wrapper of logic surrounding a conventional single-port static memory function, thus a single-port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual-port memory device would otherwise make possible.
U.S. Pat. No. 5,761,147 to Lindner et al. discloses a virtual two-port memory structure with fast write-through operation, where the virtual two-port memory structure employs a SPRAM cell.